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DNA-AFDX-664

DNA-AFDX-664
2-Channel AFDX / ARINC-664 Interface
 
The DNA-AFDX-664 is a 2 channel AFDX/ARINC 664 (including the Boeing EDE protocol) communications interface for “Cube” I/O chassis. The board may be configured as two independent channels or one dual redundant channel. The network implementation fully supports 10, 100 and 1000 BASE-T speeds. The channels may operate as a receiver, transmitter or network/bus monitor.

In input mode, the user may time tag inputs with resolutions as low as 10 microseconds. The input automatically provides error/integrity checking, though this feature may be disabled if the application requires. Receive filtering is also supported based on the VL, Port and error detection.
The Monitor mode allows the user to capture all network traffic, or may be set with automatic filtering so only the desired information is captured. The Monitor mode will also gather a variety of statistics from the bus/network. If desired, the monitor mode may be set to capture all UDP network traffic, regardless of whether it is configured based on the AFDX/664 protocol.

Transmit channels automatically configure traffic shape via Bandwidth Allocation Gaps (BAG) with 1, 2, 4, 8, 16, 32, 64 or 128 mS timing. Transmission may be based on an automatic scheduler, or in a one-shot asynchronous mode. Both Uni-cast and Multicast VLs are fully supported. The board is designed to inject various errors if desired, including logical, timing and AFDX protocol errors. The transmitter will generate consecutive Sequence Numbers or they may be user-defined.
 
Characteristics:
  • For use in “Cube” I/O chassis
  • 2 independent or 1 dual redundant channels
  • 10/100/1000 Base-T implementation
  • Transmit, Receive or Bus Monitor function
  • Consecutive or user defined sequence Numbers
  • 10 µS, 1 µS and 100 nS time tags
  • Error detection and injection
  • Extensive filtering and traffic scheduling
  • Includes support for Boeing EDE protocol
 
Technical Specifications
Configuration
Number of channels 2 fully independent or 1 dual redundant
Ethernet BASE 10, 100 or 1000 BASE-T
Channel functions Transmit, Receive or Monitor
VLs supported Up to 65535 VLs or ports per VL
Underlying Processor Freescale 8347 running DO-178 certified OS
Receive Specifications
Time tagging resolution 10 µS, 1 µS or 100 nS
Error/Integrity checking Integrity, Link-level, Sequence Number (SN) and Frame structure
Filtering VL, Port and error detection filters
Monitor Specifications
Configuration All or Filtered with or without time-tag
Error Checking Capture all, valid or invalid VLs
Statistics Gathering Counters Physical symbol, invalid preamble, invalid/ missing SFD, Frame length error, CRC
Non-AFDX UDP packets May be captured if desired
Transmit Specifications
Traffic shape via BAG 1, 2, 4, 8, 16, 32, 64 or 128 mS
Transmission scheduling 10 µS resolution schedule scheduling of VLs and ports plus a one-shot Async mode
Transmission configuration Unicast and multicast VLs
Sequence Numbers Consecutive or user-defined
Error Injection Logical errors Physical Symbol, Preamble length, Framing size and alignment, SFD, CRC
Timing errors BAG violations, Inter-frame gaps
AFDX protoco Redundancy, multiple source, port rate
General Specifications
Debugging options via Cube/RACKtangle chassis backplane or directly to board via RS-232 port
Loop back testing Loop back mode on the DNx-AFDX-664 allows automatic self-test
Operating temperature tested -40 °C to +85 °C
Vibration IEC 60068-2-6 5 g, 10-500 Hz, sinusoidal
IEC 60068-2-64 5 g (rms), 10-500 Hz, broad-band random
Shock IEC 60068-2-27 50 g, 3 ms half sine, 18 shocks @ 6 orientations
30 g, 11 ms half sine, 18 shocks @ 6 orientations
Humidity 5 to 95%, non-condensing
Power consumption 6 Watts, maximum