Technical Specifications |
General |
Number of counter/timer units |
8 |
Resolution |
32 bits |
Prescaler (per channel) |
1 (32 bits) |
Maximum frequency |
16.5 MHz for external input clock;
66 MHz for internal input clock;
33 MHz for outputs |
Minimum frequency |
no low limits |
Internal 66 MHz time base (from backplane clock signal) |
Initial accuracy: ±10 ppm
Temp drift: ±15 ppm over full temp range
Time drift: ±5 ppm year one, then lower |
On-board FIFOs, per counter |
Input: 256 x 32; Output: 256 x 32 |
Minimum pulse width |
15.15 nsec |
Minimum period |
30.30 nsec |
Pulse-width/period accuracy |
2 internal clock cycles (30 nsec) on one or multiple periods |
Debouncer circuit size |
32 bits (on GATE and CLKIN) |
Compare registers per counter |
2 |
External gates per counter |
1, programmable polarity |
External triggers per counter |
1 (shared with Gate), edge sensitive, programmable polarity |
Protection |
7 kV ESD, 350V isolation |
Input High / Low voltage |
2.0-5.0V / 0.0-0.8V |
Output High / Low voltage |
>2.0 V / <0.8V @ ±12 mA |
Power consumption |
2W |
Operating range |
Tested -40 to +85 °C |
Humidity range |
0 - 95%, noncondensing |
Vibration |
IEC 60068-2-6 |
5 g, 10-500 Hz, sinusoidal |
IEC 60068-2-64 |
5 g (rms), 10-500 Hz, broad-band random |
Shock IEC 60068-2-27 |
50 g, 3 ms half sine, 18 shocks @ 6 orientations
30 g, 11 ms half sine, 18 shocks @ 6 orientations |