Technical Specifications |
Analog Outputs |
Number of channels |
32 |
Resolution |
16-bit |
Update rate |
100 kS/s per channel;
450kS/s aggregate in non-DMA mode;
up to 1100 kS/s aggregate in DMA mode |
DSP buffer size |
2k samples (2 buffers x 1k sample) |
Type of D/A |
double-buffered |
Data transfer modes |
DMA, interrupt, software |
Accuracy |
±3 LSB max |
DNL |
±3 LSB max |
Monotonicity over temp. |
15 bits, -40 to 85°C |
Calibrated gain error |
3mV typ, 6mV max @ ±9.8V |
Calibrated offset error |
1mV typ, 2mV max @ 0.0V |
Output range |
±10V (custom ranges available) |
Output coupling |
DC |
Output impedance |
0.15Ω max |
Current drive |
±20mA min, ±320mA max for all channels |
Capacitive loads |
180 pF min |
Settling time |
10µs to 0.003% |
Slew rate |
10V/µs |
Gain bandwidth |
1 MHz |
Noise |
2 LSB RMS, 0-10000 Hz |
Output protection |
short to ground, ±15V |
Power-on state |
0.0000V ±5mV (default), user programmable |
Gain drift |
25 ppm/°C |
Digital I/O |
Number of channels |
8 inputs, 8 outputs |
Compatibility |
CMOS/TTL, 2kV ESD protected |
Power-on state |
logic zero (default), user programmable |
Data transfer modes |
DMA, interrupt, software |
Input termination |
4.7kΩ pull-up to 5V |
Output high level |
3.0V typ @ -32mA, 3.4V typ @ -16mA, 4.2V @ -2mA |
Output low level |
0.55V max @ 64mA |
Input low voltage |
0.0 - 0.8V |
Input high voltage |
2.0 - 5.0V |
Counter/Timer |
Number of channels |
3 |
Resolution |
24 bits |
Max frequency |
16.5 MS/s for external clock,
33 MS/s for internal DSP clock |
Min frequency |
0.00002 Hz for internal clock,
no low limit for external clock |
Min pulse width |
20 ns |
Output high level |
2.9V typ @ -4 mA |
Output low level |
0.5V min @ 4 mA |
Protection |
7 kV ESD, ±30V over/undershoot |
Input low voltage |
0.0 - 0.8V |
Input high voltage |
2.0 - 5.0V |
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